1. Field of the Invention
Aspects of the present invention relate to a method of and apparatus for determining a binary signal of a memory cell, and more particularly, to a method and apparatus for determining a binary signal of a memory capable of reducing an error rate of a binary signal stored in the memory cell.
2. Description of the Related Art
Memory may be categorized as a single level cell (SLC)-type memory capable of storing a 1-bit binary signal in one cell, or a multi level cell (MLC)-type memory capable of storing a multi-bit binary signal in one cell. In such a memory, a binary signal stored in a selected cell is determined by comparing a reference current generated in a reference cell operating according to a reference voltage with a cell current generated in the selected cell.
FIG. 1 is a diagram illustrating an example of determining a binary signal of one memory cell in an SLC-type memory according to conventional technology. Referring to FIG. 1, a cell current (ICELL) generated in a selected cell 101 is a drain-source current, and WL indicates a word line. A reference cell 102 is biased by a reference voltage (VREF) and generates a reference current (IREF). A comparator 103 compares the cell current ICELL output from the selected cell 101 with the reference current IREF output from the reference cell 102, and outputs the comparison result as the cell state of the selected cell 101. The cell state output from the comparator 103 may be 1 or 0. If the memory is designed such that electrons are stored in a cell in the memory, the cell state is 1. Conversely, if electrons are not stored, the cell state is 0. That is, if the cell state output from the comparator 103 is 1, the electrons are stored in the selected cell 101, and if the cell state output from the comparator 103 is 0, it the electrons are not stored in the selected cell 101.
FIG. 2 is a diagram illustrating an example of determining a binary signal of a memory cell in an MLC-type memory according to conventional technology. As an example, the MLC-type memory illustrated in FIG. 2 stores a 2-bit binary signal in one memory cell. Accordingly, in the example illustrated in FIG. 2, a cell current (ICELL) output from a selected cell 201 is determined in four divided stages. That is, a reference voltage is divided into V1, V2, and V3, and if the cell states 1, 2 and 3 output from comparators 205, 206, and 207, respectively, are all 0's to indicate that the cell current (ICELL) generated in the selected cell 201 is less than a first reference current (I1) output from a first reference cell 202 biased by V1, the bits stored in the selected cell 201 are recognized as 00. If the cell current is between the first reference current (I1) and a second reference current (I2), the cell states 1, 2, and 3 output from the comparators 205, 206, and 208, respectively, are 100, and thus the bits stored in the selected cell are recognized as 10. If the cell current is between the second reference current (I2) and a third reference current (I3), the cell states 1, 2, and 3 output from the comparators 205, 206, and 208, respectively, are 110, and thus the bits stored in the selected cell are recognized as 01. If the cell current is equal to or greater than the third reference current (I3), the cell states 1, 2, and 3 output from the comparators 205, 206, and 208, respectively, are 111, and thus the bits stored in the selected cell are recognized as 11.
In this way, the binary signal stored in each memory cell is determined based on the cell state obtained by comparing a cell current output from a selected cell with one or more reference currents generated in one or more reference cells according to the number of bits stored in the memory cell.
However, while reading a binary signal from a selected cell, an error may occur in the binary signal read from the selected cell due to noise caused by any of a variety of reasons. In order to prevent an occurrence of this error, error correction techniques have been suggested. An example is a method of adding parity information. However, when parity information is added, part of a data area for storing data in the memory must be allocated, thereby decreasing available user data areas.